Does anyone know how to get standard cells through lvs??

I'm drawing a mixed-mode design vith virtuoso XL and would like to use digital standard cells provided by vendor.
For these standard cells vendor provides layout views that have only diffusion, n-well and metal1 layers + pins visible.
I'm using calibre to do LVS checks.

Problem arises when calibre tries to extract the standard cells. More precisely, it cannot recognize standard cells.
I guess, it is trying to compare them on the transistor level, but fails because the layout views are incomplete.
I've tried to turn on recognize all gates option from LVS options Gates tab, but this doesn't help.
There must be a way to tell LVS checker that standard cells are OK, do not bother to check them, but how to do this?