Visjnoe
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Dear all,
in the meantime, I found this paper already:
Dong-Hee Kim and Jin-Ku Kang, "A 1.0Gbps Clock and Data Recovery Circuit with Two-XOR Phase-Frequency Detector",AP-ASIC 2000.
It looks promising, but I don't think their approach guarantees frequency lock with a random (NRZ) data input... it's just a feeling (has to be verified). There are also no measurement results in there.
Regards
Peter
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