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Tommy

Junior Member

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Posts: 19
Tokyo, Japan

Warning from Spectre
Jul 2^nd, 2007, 9:46pm

Hi ,
I get this warning from spectre when simulating a voltage multiplier circuit :

The bulk-drain junction leaves the linearized region.
Warning from spectre at time = 780.473 ns during transient analysis `tran'

I see that at this time point, the current into the bulk of PMOS is indeed very large (above 25mA)

Is this a warning sufficient to judge latch-up of the circuit?

Tnx
Tom

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« Last Edit: Jul 03^rd, 2007, 1:25am by Tommy »

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Unique Junior Member Offline Posts: 13 Russian Federation	Re: Warning from Spectre Reply #1 - Jul 5^th, 2007, 11:13pm Hi, Tommy! Sorry for my maybe inappropriate question, but what kind of ciruits You design?
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boe

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Posts: 615

Re: Warning from Spectre
Reply #2 - Jul 6^th, 2007, 2:32am

Hi Tommy,
Tommy wrote on Jul 2^nd, 2007, 9:46pm:

I see that at this time point, the current into the bulk of PMOS is indeed very large (above 25mA)

In a process with an n-well in p-substrate, every PMOS includes a parasitic pnp; the PMOS n-well (bulk) is the base of this pnp.
So you get a current from PMOS S/D to p-substrate that is beta (current gain of the pnp) times your bulk (i.e. base) current!

BOE

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Geoffrey_Coram

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Massachusetts, USA

Re: Warning from Spectre
Reply #3 - Jul 6^th, 2007, 4:59am

Boe -
But that parasitic PNP is generally not included in the spice models.

Tommy -
I find it odd that you got a notice that it was leaving the linearized region; do you also have an earlier warning that it is entering the linearized region? When it is in the linearized region, then the current is inaccurate (linearized instead of the true exponential). Of course, immediately after it exits the LR, it will still have a very large bulk current.

Whether you get latch-up or not depends on how the 3rd terminal of the BJT (the source of the MOS in this case) is connected. However, in the case that the drain-bulk current is linearized, that means that the junction is forward biased (p drain higher than nwell bulk). Usually, latch-up occurs when the junction is reverse-biased (for a PMOS, avalanche current from bulk to drain lowers the bulk potential such that the source-bulk junction is forward-biased).

The impact ionization current is responsible for sustaining latch-up, so you can't just measure the external base/bulk current and multiply this by beta. (BVceo is sometimes measured by detecting where the base current changes sign!)

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boe Community Fellow Offline Posts: 615	Re: Warning from Spectre Reply #4 - Jul 6^th, 2007, 6:39am Geoffrey_Coram wrote on Jul 6^th, 2007, 4:59am: Boe - But that parasitic PNP is generally not included in the spice models. True. However, if you have significant bulk current (forward biased Drain/Bulk diode), you must take the pnp into account. BOE
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