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morozmoroz

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I need everything be
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Ukraine, Kiev, Melexis

switch model
Jul 03^rd, 2007, 8:10am

Hello, guys!

I have such problem:
I try to make instance of switch module in verilogA code like this:
switch #(.vth(0.5)) sw1 (in,out, cp,cn);

But when I run simulation Cadence just says me that parameter vth is not legal for swith. I have tried to
find description of this module but found only in veriaref.pdf that vth is legal.
So, could you help me with this - where I can find description of parameter for all possible basic includive
modules? (and if possible - where are they in standart Cadence hierarchy?).
Big thanks in advance, Denis.

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boe

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Re: switch model
Reply #1 - Jul 3^rd, 2007, 10:59am

Hi Denis,
morozmoroz wrote on Jul 3^rd, 2007, 8:10am:

I try to make instance of switch module in verilogA code like this:
switch #(.vth(0.5)) sw1 (in,out, cp,cn);

Which implementation of switch do you use?
For your code to work, it must have a parameter vth... analogLib.switch, for example, does not have vth, but vt1 & vt2 (cf. CDF parameters of the cell).

Hope this helps...
BOE

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morozmoroz

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I need everything be
in behavior:)

Posts: 7
Ukraine, Kiev, Melexis

Re: switch model
Reply #2 - Jul 4^th, 2007, 12:25am

Yes, I have tried and vt1, vt2 parameters too, but the error is the same. that's why i began to think that this switch is not from analogLib, may be it is from some internal directory of VerilogA compiler. I made like this because I found it in Ken book (The deigners guide to VerilogAMS) about resistor. But I have not found resistor name in analogLib, but in sample lib. So, now I am absolutely confused.
Look forward to hear from anyone

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boe Community Fellow Offline Posts: 615	Re: switch model Reply #3 - Jul 5^th, 2007, 2:23am Hi Denis, The cell "analogLib switch" (used in a schematic) is netlisted as "relay", so if you use (say) relay #(.vt1(0.5), .vt2(1)) sw1 (in,out, cp, cn); it simulates... I haven't checked the result though... BOE
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boe Community Fellow Offline Posts: 615	Re: switch model Reply #4 - Jul 5^th, 2007, 5:24am morozmoroz wrote on Jul 4^th, 2007, 12:25am: [...] But I have not found resistor name in analogLib, but in sample lib. So, now I am absolutely confused. "analogLib res" is netlisted to a Spectre "resistor", as "analogLib switch" is mapped to a Spectre "relay"... This is defined using CDF parameters. BOE
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morozmoroz New Member Offline I need everything be in behavior:) Posts: 7 Ukraine, Kiev, Melexis	Re: switch model Reply #5 - Jul 6^th, 2007, 1:06am Thanks a lot, especially to boe. This forum is great
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