Hello, guys!
I have such problem:
I try to make instance of switch module in verilogA code like this:
switch #(.vth(0.5)) sw1 (in,out, cp,cn);
But when I run simulation Cadence just says me that parameter vth is not legal for swith. I have tried to
find description of this module but found only in veriaref.pdf that vth is legal.
So, could you help me with this - where I can find description of parameter for all possible basic includive
modules? (and if possible - where are they in standart Cadence hierarchy?).
Big thanks in advance, Denis.