Hi, i'm trying to simulate a dc-dc buck converter with a digital control. the power cell is written in vhdl-ams, the digital control in vhdl.
When i try to simulate in cadence, the simulation starts, but the power cell appears disconnected from the digital control.
i try to use connect models, but the code in vhdl-ams is written so that the output of the power cell is std_logic, and correspond to the input of the digital control, so it doesn't work....