aaron_do
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Hi eng,
in the swept PSS, when you look for 1 dB compression, rather than selecting output port, you can also select differential nets for voltage. There's really only one other net to check which is the drain of your input transistor. Most likely it is not causing compression since it is a low impedance node.
Changing the tail current to an ideal current source will not tell you whether or not the compression is caused by the tail current since the tail current is supposed to imitate an ideal current source.
I believe based on the information that it is indeed the tail current that is limiting your P1dB. You load resistance is 40 nH which at 400 MHz is only 100 ohm. Therefore given your voltage gain, your Gm is about 0.141. Since your tail current is 800 uA, the 1 dB compression would be roughly 0.0567 Vpk (800u/0.141) which is -35 dBm into 50 ohm. If this is really the case, then you should increase your load resistance. This can be done by replacing your load inductors with a resistor, or better yet, a PMOS load with CMFB (better P1dB). You should then lower Gm to meet voltage gain requirements.
Sorry if my calculation is wrong...i kinda rushed it.
BTW, if this is a fully integrated design, you don't really need to worry about S21, simply load the LNA with the mixer input impedance and find the voltage gain.
cheers, Aaron
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