Hi,
I'm working on a low power (sub mW) differential LNA around 400 MHz. The single ended version had ~-15 dB P1dB but this diff one has ~-37. It is too low. I wonder how to improve this linearity without burning too much current and loosing too much gain.

The following recent post talks about baseband amplifier where tail current source is the reason of IIP3 loss.
http://www.designers-guide.org/Forum/YaBB.pl?num=1182847323
I think this is the case for my design as well. But I need experienced guidance on what kind of improvements I should do.

thanks

I can only say that the gain will affect linearity. you can reduce Q to compensate linearity.

Hi eng,

in the swept PSS, when you look for 1 dB compression, rather than selecting output port, you can also select differential nets for voltage. There's really only one other net to check which is the drain of your input transistor. Most likely it is not causing compression since it is a low impedance node.

Changing the tail current to an ideal current source will not tell you whether or not the compression is caused by the tail current since the tail current is supposed to imitate an ideal current source.

I believe based on the information that it is indeed the tail current that is limiting your P1dB. You load resistance is 40 nH which at 400 MHz is only 100 ohm. Therefore given your voltage gain, your Gm is about 0.141. Since your tail current is 800 uA, the 1 dB compression would be roughly 0.0567 Vpk (800u/0.141) which is -35 dBm into 50 ohm. If this is really the case, then you should increase your load resistance. This can be done by replacing your load inductors with a resistor, or better yet, a PMOS load with CMFB (better P1dB). You should then lower Gm to meet voltage gain requirements.

Sorry if my calculation is wrong...i kinda rushed it.

BTW, if this is a fully integrated design, you don't really need to worry about S21, simply load the LNA with the mixer input impedance and find the voltage gain.


cheers,
Aaron

Hi Aaron,
Your replies are very enlightening for me. Thank you so much. I attached vgain(xf) nf(noise) s11(sp) and p1dB(swpt pss) graphs. p1dB is -38 dB.
Which of the followings is more effective to improve linearity? If there are other ways could you add them to the list. Or if anything is wrong correct it as well.
1) Reducing gm by decreasing W and increaing Vbias of input transistors -> Less Gain more NF
2) Increasing tail current (it was 800u total 400u each branch) -> More power
3) Using resistors as load instead of ind.s -> More NF.

Does cascode transistor has anything to do with linearity?
Does the L (I'm using 500n in 0.18um process) of tail current source contribute to linearity?

Thanks