Hi,

When realizing a successive approximation type of converter, one often uses a capacitive DAC.
The limitation here is usually mismatch, particularly due to the large variations on the smallest
caps which are 2^N times smaller than the largest ones, and the standard method is to choose a large
enough unit element cap, but this gives too much capacitance => more power.

From time to time, people talk of using multiple unit caps in series to realize the smaller caps in the C-DAC.
For instance, an 8-bit C-DAC may have 16 unit caps in parallel for the largest element and 16 unit caps in series
for the smallest one (to exaggerate, as this would still not be a good solution).

How does one control the intermediate high-Z nodes now? There will be several problems including charge-deposition
during the ion etch process on these plates. If one were to tie a reverse-biased diode to these plates, then the leakeage current
of these would wreak havoc at these high-Z nodes.

Is there a way around?

Thanks
Vivek

ACWWong wrote on Jul 17^th, 2007, 3:48am:


Hi ACWWong,

Could you please explain a bit more? You say that there is no problem if the bottom plate is contacted up to the same level of metal as the
top plate. But it is contacted to a different piece of metal. Does this not result in charge accumulation still?

Also, are there any other issues except the ion etching one?

Thanks very much.
Vivek

Vivek - I have used a "splitting capacitor" between two five bit cap dacs to create a 10 bit cap dac for a sar.  I think bottom plate capacitance will prevent you from doing more than one splitter cap because you need the bottom plate parasitic to be on the comparator input to prevent non-linearities.  

I don't remember the details, but handling the high Z node was easy.  I think I just connected both sides of the splitting capacitor to the same potential when sampling the input.  It worked fine.  

rg

Hi ACWWong,

I am afraid I have no way of accessing this paper as my subscription is only to JSSC. Is there
some other place where I may see the same system that you desribe? I would be very glad to
have it for reference. I don't know for sure if I will have MIM caps or only poly-poly,
but it would be good to have a potential solution.

Hi Rob,

I have seen the paper by Chen and Brodersen but as you pointed out, they show no technique
for setting the intermediate nodes. I think switching them to the common-mode during sampling
may not work that well for 2 reasons:

1. The additional junction capacitance at the nodes will be a problem as will the leakage from these
2. The overall sampling capacitance will increase quite a lot. Chen keeps those caps in series while sampling
so as to reduce overall capacitance as much as possible.

I am not using calibration, but trying to use the series caps to improve matching.

Thanks & Regards
Vivek

I think both balanced interconnection suggested by ACWWong and  junction diode are both required to avoid MiM damage during plasma process. The junction diode can not be neglected because the metal area for top & bottom plate is not easy to be identical, which induces potential difference on MiM.