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hanm

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Specifications of regulators in SOC
Jul 26^th, 2007, 1:39am

Hello experts:
I have question on how to define the regulator specifications(especially parameters such as psrr, noise etc.) in SOC. For example, this regulator may be used in a 2.4G transceiver, the IF is 2MHz, and the digital circuits run at a clock frequency 16MHz. So I think the most critical psrr request must ocuur at those frequency points, I guess. But how degree the value is, and what's the general sence of the value?
Any comments are welcome!

hanm

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HdrChopper

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Re: Specifications of regulators in SOC
Reply #1 - Jul 26^th, 2007, 6:55pm

Hi Hanm,

I'm not an expert, but from my experience I can tell you some points I would consider during the regulator's design phase:

1) Output impedance over frequency. This is related to what you mentioned as critical frequencies for the regulator performance. I should look for the lowest output impedance possible, and in particular at those frequencies of interest. Therefore, the regulator's loop will have to be as wide-band as possible --> that will compromise your stability though. So there is a clear trade-off between stability and output impedance.

2) PSRR can be quantified by applying an ac source on the regulator line and looking at how much attenuation do you get over frequency in the regulated line. Again a wider regulator will guarantee better rejection at high frequency but compromise stability. The PSRR performance will be also compromised as the supply voltage get closer to the regulated voltage, that is your worst case condition.
I usually use -40 to -60dB of attenuation at DC, but that depends on the type of regulated circuits and how much noise they generate.

3) Load sensitivity: defined as the ΔVREG/ΔILOAD.

4) Supply sensitivity: ΔVREG/ΔVCC

Hope this helps
tosei

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hanm

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Re: Specifications of regulators in SOC
Reply #2 - Jul 26^th, 2007, 10:02pm

Hi tosei:

Thanks for your response!

I totally agree with you these points should be taken care of during a regulator design phase!

From the lists item 2, you usually have a 40 to 60 dB psrr at dc. I want to know why it's this value, why not 20dB or 80dB psrr. From which point you decide of this value? Moreover,generally the psrr of a regulator is with a high pass frequency response, value at dc is not the most consider point, how to define other frequency point value is also I care of.

hanm

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mg777 Senior Member Offline Posts: 131	Re: Specifications of regulators in SOC Reply #3 - Jul 26^th, 2007, 10:14pm Linear regulators are used in circuits such as PLL VCO's, but is it true that SoC regulators are mostly of the switching variety? If so, I'd also include ripple, spurs, and performance derating for external passives. On tosei's list, I'd place maximum emphasis on ΔVREG/ΔILOAD. M.G.Rajan
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Visjnoe

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Re: Specifications of regulators in SOC
Reply #4 - Jul 27^th, 2007, 12:03am

Dear Hanm,

I think you pose a good question with regard to the PSRR specification. In most projects I've done, PSRR (for all building blocks, not just the regulators) is specified 'ad hoc' by the customer (or so it seems).

I've always insisted on treating this specification using a more structured approach. When it comes to PSRR, there are basically 2 important variables:
1. the frequencies of interest: you can never be entirely sure which frequency will eventually bug you the most, but having a look at digital clock frequencies/switching frequencies etc. (and their harmonics!) that are actually present on your chip is probably the most sensible thing to do. Also have a look at the switching frequencies of external regulators (if any).

2. when it comes to the actual PSRR specification at a certain frequency, I would suggest you try to analyze (by hand) the effect of ripple on the supply on the performance of your block. This provides the most insight.
If handcalculations are too tedious, make PSRR a part of the behavioral model of your building blocks. Set PSRR specifications of your building blocks and examine relevant system metrics (e.g. EVM for a WLAN receiver). Adjust the PSRR specifications until the system impact is as low as you want.

Regards

Peter

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HdrChopper

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Re: Specifications of regulators in SOC
Reply #5 - Jul 27^th, 2007, 5:21am

I think Peter and mg777 brought up very good points.

Other frequency points -different from DC- in your PSRR curve over freq will be defined by your loop freq response (the unity gain frequency will somehow define at which frequencie your PSRR will start getting reduced).
In addition, depending on the external passive components you will have in your applications, say a bypass cap from supply to GND, very high frequencies on the supply line might not be a problem so you should not worry about a very high PSRR at those frequencies.

tosei

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