loose-electron
Senior Fellow
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Best Design Tool = Capable Designers
Posts: 1638
San Diego California
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Hey all -
give me your take on this one ---
A generic ring oscillator PLL, if you look at the control systems equations, the input reference clock, and the loop BW have nothing to do with each other.
That said, most loops I have designed in the past have loop BW's that were less than the clock rate coming into PFD.
If you go to a higher loop BW than the reference clock frequency what issues arise and become problematic?
Lets say for sake of argument a reference clock of 1MHz and a loop BW of 10 MHz. The phase correction will be much less smooth, but if the zeta/damping is set properly it still should work fine, just look a lot more like a discrete corrections on the system rather than a linear response.
Any opinions or expereinces here to share?
thanks, Jerry
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