Hello,

This is my first PLL design. After finishing every block in the loop, now I try to do a transient analysis for the whole loop at transistor level to check the locking.

1. the waveform of the control voltage of the VCO (Vcont):  say reference frequency is higher than the divider output frequency, then the charge pump charges the caps of LPF.  What I see is that Vcont goes up during charging period, and drops sharply during tri-state period. Is it normal for PLL transient simulation ? My LPF is simply C1+R1//C2, R1 is about 48K, which is estimated by equations of linear modeling.

I then replace the LPF with just one capacitor to check whether there is big leakage path. No problem with that.  Also I notice that the voltage drop on R1 will cause charge-sharing between C1 and C2 during tri-state period, which makes the Vcont drop. Is that correct ?    

2. I also wonder how long I should setup the simulator time ? In my design, the reference frequency is 2MHz,  loop-BW is about 100K.  Any good estimation about the locking time needed based on above information ?

3. More general question : can anyone share some ideas or reference on PLL noise/stability simulation ?

Thank you so much!

Yp