Designer’s Guide Community

vivkr

Community Fellow

Offline

Posts: 780

simulating DNL of ADC macromodels
Aug 16^th, 2007, 6:58am

Hi,

I was wondering if there was any efficient method of simulating the DNL of a given ADC.
I use MATLAB to model my ADC schemes. For lab measurements of course, one has to use
the histogram method with sinewave inputs for testing as it is the only fast method.

However, in simulation, one can truly provide a set of DC input levels to assess the impact of
element mismatch on different ADC configurations. This method has the advantage that the
underlying distribution is uniform and not the bathtub distribution of a sinewave which causes
nightmares in terms of the number of points needed for a given confidence level.

I tried to use the histogram method and looked at the code distribution of the bins, taking the
deviation from the average value as an indication of DNL as the code density per bin will be proportional
to the bin width. However, this method cannot catch nonmonotonicity in my opinion because I could
theoretically shift the ADC bins all around randomly, keeping the bin widths the same and it would appear
that the ADC has no DNL.

What would be a better way to measure DNL in macromodel simulations?

Regards
Vivek

Back to top

IP Logged

sheldon Community Fellow Offline Posts: 751	Re: simulating DNL of ADC macromodels Reply #1 - Aug 17^th, 2007, 7:04pm Vivek, You can do a dc sweep at the input to determine the DNL of an data converter. Look at the DNL tester, adc_dnl_8bit in ahdlLib as an example of how to do this. Also since there is now a link from Spectre RF to Simulink, you can use adc_dnl_8bit as the testbench for your macromodel. Best Regards, Sheldon
Back to top	IP Logged

vivkr

Community Fellow

Offline

Posts: 780

Re: simulating DNL of ADC macromodels
Reply #2 - Aug 19^th, 2007, 11:44pm

Hi Sheldon,

Thanks for pointing out this very interesting reference to ahdlLib. I had never looked at it until now.
It turns out that I use the same method in my MATLAB model. My concern is simply about the
ability of this scheme to detect anomalies in the DNL pattern. For instance, I might in principle map
around all the code steps randomly keeping the code width the same (as an extreme case) and the histogram
would still look the same. Of course, real converters ought not to have such large errors otherwise it
would be pointless to try to measure the DNL.

However, I am still a bit doubtful if the histogram method can detect mild nonmonotonicities. It seems
to me that this is not really the case if the codes around the center of the range get swapped around.

Do you have any comments or references on this point which might help me?

Thanks
Vivek

P.S. I would not tie a Spectre model to MATLAB. The latter is very fast with vector operations, can't say
if the speed would be preserved if one were to do a pipe between the 2.

Back to top

IP Logged

sheldon

Community Fellow

Offline

Posts: 751

Re: simulating DNL of ADC macromodels
Reply #3 - Sep 7^th, 2007, 3:15am

Vivek,

Just a comment on the speed, it would be straight forward to re-write the
testbench into Verilog-AMS. Since Verilog-AMS supports analog, discrete-time
simulations there is not a large speed penalty. There was a tutorial/paper at
BMAS a couple of years ago by Jonathan David that included a discussion of
modeling Pipeline ADC with Verilog-AMS. The other advantage of writing the
model in Verilog-AMS is that it can be used for mixed-level simulations. The
limit of your present approach is that you need to start over again at circuit
design.

I have not thought through the issue of non-monotonicity with the the
histogram method in detail. However, it seems like in the limit it should
have the same accuracy as the ramp method. The issue is the number
of samples required to achieve accuracy. With the ramp the samples are
evenly distributed across the entire input range. On the other hand, the
histogram method there are less samples at the msb transition so you need
to run more tests to equivalent accuracy.

Best Regards,

Sheldon

Back to top

IP Logged

vivkr

Community Fellow

Offline

Posts: 780

Re: simulating DNL of ADC macromodels
Reply #4 - Sep 7^th, 2007, 3:43am

Hi Sheldon,

Thanks fdr your detailed reply. I did some thinking and I agree with you that the histogram method
does not have such a big limitation as far as nonmonotonicity is concerned, unless the errors are really
really bizarre, almost unphysical in nature.

And when I speak of the histogram method, I am speaking of a ramp-based histogram method.
One uses sinewaves in real life because precise ramps are almost impossible to generate. However,
in a simulation setup, that is trivial. This cuts down the number of points seriously because the
points on a ramp have uniform density.

I will think about Verilog-AMS, but I think that MATLAB is much better if one is only modelling
higher-level issues, such as impact of capacitor mismatch or finite opamp gain. In MATLAB, one can
avoid the trouble of generating the ramp in time-domain but generate a virtual ramp in the input-domain
by using a vector input. As MATLAB is very good at vector match, calculating the output for 10^5 input
points does not take so much more time than calculating it for 10^3, as everything runs in parallel.

I am able to simulate random mismatch variation for 1000 runs in a matter of 1 hour or so

Regards
Vivek

Back to top

IP Logged