The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Oct 31st, 2024, 5:08pm
Pages: 1
Send Topic Print
current steering logic(CSL) buffer (Read 7770 times)
dandelion
Community Member
***
Offline



Posts: 98

current steering logic(CSL) buffer
Sep 03rd, 2007, 11:54pm
 
Hi,
In the mixed signal design, to reduce the di/dt noise, CSL(current steering logic)attract more and more attention.

I am not familar with the CSL and I want to know is there any mature product of mixed mode IC used this technique which ahve replaced conventional static inverter?

Thanks
Back to top
 
 
View Profile   IP Logged
Visjnoe
Senior Member
****
Offline



Posts: 233

Re: current steering logic(CSL) buffer
Reply #1 - Sep 4th, 2007, 10:53am
 
Dear,

read any decent paper on SerDes RX/TX (PCI Express, SONET, XAUI...) and you will find lots of implementation examples.


Regards

Peter
Back to top
 
 
View Profile   IP Logged
dandelion
Community Member
***
Offline



Posts: 98

Re: current steering logic(CSL) buffer
Reply #2 - Sep 4th, 2007, 6:39pm
 
Visjnoe wrote on Sep 4th, 2007, 10:53am:
Dear,

read any decent paper on SerDes RX/TX (PCI Express, SONET, XAUI...) and you will find lots of implementation examples.


Regards

Peter

Hi,Peter,
Thanks for the reply.

I guess you mean the CML logic( current mode logic). Here, my question is I need the CSL logic buffer to replace the oringinal static inverter buffer(CMOS level). So, the requirement is critical for the low power, high driver capability. I found the Vol and Voh spec of my CSL logic implementing cmos level is  not good as static inverter, especially it would be worse when the load sink or source some current. Although its di/dt noise is indeed excellent, I wonder if any product use this technique to implement a CMOS level.

Thanks
Dandelion
Back to top
 
 
View Profile   IP Logged
email_gz
Junior Member
**
Offline



Posts: 31
gaoz.mail@gmail.com
Re: current steering logic(CSL) buffer
Reply #3 - Nov 11th, 2007, 9:50pm
 
Hello all:
       I think current steering logic(CSL) buffer  is just CML. Except CML Driver, maybe Voltage Mode Driver can be used for lower power, but this type of driver is hard design becasue of Z match,and often have small output swing. AMD HT3 IO-link use Voltage Mode Driver with current mode Channel-Pre-Eq.
Back to top
 
 
View Profile email_gz email_gz   IP Logged
fonseca.ha
Junior Member
**
Offline



Posts: 28
UK
Re: current steering logic(CSL) buffer
Reply #4 - Feb 2nd, 2008, 10:27am
 
Hello All,
Does anyone has a reference about CSL. I didn't found what is the when compared to CML.
Cheers,
Humberto
Back to top
 
 
View Profile   IP Logged
loose-electron
Senior Fellow
******
Offline

Best Design Tool =
Capable Designers

Posts: 1638
San Diego California
Re: current steering logic(CSL) buffer
Reply #5 - Feb 26th, 2008, 6:45pm
 
Last I checked -

CSL is the same as differential CML

If you research ECL (Emitter coupled logic) designs you will find info on ground referenced CML.
(Look around for data on MECL 10,000 - Motorola's old ECL stuff)

That is an old bipolar version of singled ended CML.

THere exist level shift and convert circuits between CSL and vanilla CMOS logic, amplification to recreate a rail to rail logivc level, in essence.
Back to top
 
 

Jerry Twomey
www.effectiveelectrons.com
Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical
View Profile WWW   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.