Hi，
We are developing a mixed signal project. Its goal is to fully integrate from the RF pre-amplifier(like LNA) to the base band signal part which is TTL/CMOS output.

I know, we should consider the intrinsic device noise and the switching di/dt noise simultaneously.  I want to know, which one noise will determine the noise floor?
Is the di/dt noise is in same order or less/larger than the device intrinsic noise (i.e., input referred total noise)?

Would you pls. share with me your experience on this topic?

Thanks

Hi Dandelion,

Among the things Berti pointed out one important is the system bandwidth vs the di/dt noise harmonic components. Obviously having a bandwidth for the front end signal much lower than the di/dt first harmonic will probably determine the device noise will be the one dominating, assuming the di/dt noise somehow goes through such bandwidth. Different scenario (and more difficult to predict) would be if such di/dt noise is generated after the bandwidth is limited in your system.
Generally, if you do a good job in floor planning and separate digital from analog supply lines, keep good isolation between those lines and use substrate guard rings and other (digital) noise reduction techniques, your device noise might dominate the signal´s noise.

Regards
tosei

Hi all,

I agree with the comments from Berti and Tosei.

Nonetheless, it should be stressed that most likely distance will provide but very limited help. If you're using an epitaxial process on top of an heavily doped bulk, distance does not help at all. If the chip is manufactured with lightly doped material things are more complex. For instance, putting the "bad" and the "good" guys in opposite corners looks like a large distance, but the actual isolation will be limited as the noise will use the pad and scribe rings to reach the victim instead of following a straight, more resistive, line.

You might want to read the following to know more about noise reduction strategies:

T. Blalack, “Design Techniques to Reduce Substrate Noise,” in Analog Circuit Design: Volt Electronics; Mixed-Mode Systems; Low-Noise and RF Amplifiers for Telecommunication, J. Huijsing, R. v. d. Plassche, and W. Sansen, Eds. Boston: Kluwer Academic Publishers, 1999, pp. 193-218.

... more specifically an old publication of mine regarding manufacturing impact:

F. J. R. Clément, “Technology Impacts on Substrate Noise,” in Analog Circuit Design: Volt Electronics; Mixed-Mode Systems; Low-Noise and RF Amplifiers for Telecommunication, J. Huijsing, R. v. d. Plassche, and W. Sansen, Eds. Boston: Kluwer Academic Publishers, 1999, pp. 173-192.

Regarding Tosei's comment about frequency planning, I've encountered in practive very tricky issues because digital noise will occupy a very wide band. Especially, due to cycle-to-cycle variations, you will get noise at lower frequencies than your digital clock.

Eventually the answer to your question also connects with the mechanism(s) through which interfering noise -- and that could also be analog or RF noises, very different from digital di/dt... -- will impact the specifications of your victim blocks (intermodulation with carrier frequency, with adjacent channels in reception, etc.)

For a good overview of the problematic, I'd suggest reading the following:

M. Á. Méndez Villegas, “Contribution to the Characterization of Substrate Noise and its Impact on Radio Frequency CMOS Circuits,” Thesis Dissertation, Universitat Politècnica de Catalunya, Barcelona, 2007.

Sorry for blowing the cold, but I've seen many expert RF designers stucked with significant design failures. For instance where 20 devices of a multi-million device chip were unexpectedly causing significant degradations on the DCO of an RF design, and not only spurs

So, you will certainly have to design very carefully to guard against instrinsic noise issues, but most likely you will have to deal with tricky interferences as well.

I'd be happy if I can provide some more help but that would require to know more of the design specifics (package characteristics, I/O constraints/strategy, ESD structures, manufacturing process, ...)

Best Regards,

François