we know, to reduce the di/dt noise in the mixed signal IC, the CSL(current steering logic) and FSCL logic attract moe and more attention. According the information i got by now, it seems that these two logic is only suitable as the internal logic cell. It seems not suitble as the interface buffer which need to dravie the large load.

Would anyone pls. share some information with me? Is it correct for my understanding?

Thanks