Hi

Please could you say more precisely what you are trying to do, and the errors that you obtain?

Very briefly, the command file is a spice file. It can be very simple (for instance if your simulation has a 'top' that is Verilog-A(MS)).
The do file is a Tcl script file. You don't need this if you are using vasim in GUI mode (though it will make loading/running the design quicker).

Just a quick example for a Verilog-AMS simulation:
1. Create a library, e.g., "valib WORK"
2. Compile your design, e.g., "valog design.va"
3. Run vasim. The "Compiled HDL" button should be selected for Top Design.
4. Select your Design Unit from the list.
5. For the Command File, click New, and check the Analysis that you want to perform.
6. Click Load.
7. Assuming all has gone well so far, click on the Run All button.

If you still have problems, try contacing Mentor support.

Regards
Paul