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rakeshkumar New Member Offline Posts: 3	problem in simulation Oct 09^th, 2007, 5:08am i m using verilogA code for opamp in cadence enviornment my output is getting saturated the reason of this i coudn't find i also want to view the internal node cout any suggestion plz!!!!!!!!!!!!!!!!!
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Stefan Senior Member Offline Posts: 124	Re: problem in simulation Reply #1 - Oct 9^th, 2007, 5:17am Hi rakesh(?), a) your "!" key seems to be stuck. b) How to judge about your code if you don't provide it ? c) Think about load. d) What the heck is cout ? e) Hello and thank you is good to appear polite.
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rakeshkumar

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Posts: 3

Re: problem in simulation
Reply #2 - Oct 9^th, 2007, 5:21am

this is my code

'define pi=3.141592

//---------------
//opamp
//-operaional amplifier
//
// vin_p, vin_n: differential input voltage[V,A]
// vout : output voltage[v,A]
// vref : reference voltage[V,A]
// vspply_p : positive supply voltage [V,A]
// vspply_n : negative supply voltage[V,A]
//
//INSTANCE parameters
// gain=gain[]
// freq_unitygain=unity gain frequency[Hz]
// rin=input resitance[ohms]
// vin_offset=input offset voltage referred to negative[V]
// ibias=input current[A]
// iin_max=maximum current[A]
// slew_rate=slew rate[A/F]
// rout=output resistance[Ohms]
// vsoft=soft output limiting value[V]
//
//
MODEL parameters
//{none}
//

module opamp(vout,vref,vin_p,vin_n,vspply_p,vspply_n);
(gain,freq_unitygain,rin,vin_offset,ibias,imax,
slew_rate,rout,vsoft)
node[V,I] vout, vref,vin_p,vin_n,vspply_p,vspply_n;
parameter real gain=835e3;
parameter real freq_unitygain=1e6;
parameter real rin=1e6;
parameter real vin_offset=0;
parameter real ibias=0;
parameter real iin_max=100e-6;
parameter real rsrc=0.5e6;
parameter real rout=80;
parameter real vsoft=0.5;
{
real c1;
real gm_nom;
real r1;
real vmax_in;
real vin_val;

node[V,I] cout;

initial{
c1=iin_max/(slew_rate);
gm_nom=2*pi*frq_unitygain*c1;
r1=gain/gm_nom;
vmax_in=iin_max/gm_nom;
}

analog
{

vin_val=V(vin_p,vin_n)+vin_offset;

//
//Input stage.
//
I(vin_p,vin_n)<- (V(vin_p,vin_n)+vin_offset)/rin;
I(vref,vin_p)<- ibias;
I(vref,vin_n)<- ibias;

//
//GM stage with slewing
//
I(vref,cout)<-V(vref,cout)/100e6;

if(vin_val>vmax_in)
I(vref,cout)<- iin_max;
else if(vin_val< -vmax_in)
I(vref,cout)<- -iin_max;
else
I(vref,cout)<- gm_nom*vin_val;

//
// Dominant Pole.
//
I(cout,vref)<-ddt(c1*V(cout,vref));
I(cout,vref)<-V(cout,vref)/r1;

//
//Output stage.
//
I(vref,vout) <- V(cout,vref)/rout;
I(vout,vref) <- V(vout,vref)/rout

//
//Soft Output Limiting.
//
if (V(vout)>(V(vspply_p)-vsoft))
I(cout,vref)<- gm_nom*(V(vout,vspply_p)+vsoft);
else if(V(vout)<(V(vspply_n)+vsoft))
I(cout,vref)<- gm_nom*(V(vout,vspply_n)-vsoft);
}
}

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Geoffrey_Coram

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Posts: 1998
Massachusetts, USA

Re: problem in simulation
Reply #3 - Oct 9^th, 2007, 6:15am

rakeshkumar wrote on Oct 9^th, 2007, 5:21am:

this is my code
'define pi=3.141592

That's silly. Just use `M_PI from constants.h

Quote:

module opamp(vout,vref,vin_p,vin_n,vspply_p,vspply_n);
(gain,freq_unitygain,rin,vin_offset,ibias,imax,
slew_rate,rout,vsoft)
node[V,I] vout, vref,vin_p,vin_n,vspply_p,vspply_n;

I'm not familiar with that notation. I'm expecting to see
inout vout, vref,vin_p,vin_n,vspply_p,vspply_n;
electrical vout, vref,vin_p,vin_n,vspply_p,vspply_n;

and then you can just add "cout" to the lists of pins.

Actually, reviewing the code further: you're not using Verilog-A. You've got {} instead of begin/end; you've got "<-" where I expect "<+".

Also, your "initial" should probably be coded inside the analog block (as @initial_step -- or not, most compilers are smart about it now); otherwise, some simulators may tell you that the variables assigned there are digital variables and may not let you use them elsewhere.

The last time someone on this forum had a problem with the op-amp, it turned out that the supply pins weren't connected properly.

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If at first you do succeed, STOP, raise your standards, and stop wasting your time.

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rakeshkumar

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Posts: 3

Re: problem in simulation
Reply #4 - Oct 9^th, 2007, 7:21am

this is my verolog-A code

'define pi=3.141592

//---------------
//opamp
//-operaional amplifier
//
// vin_p, vin_n: differential input voltage[V,A]
// vout : output voltage[v,A]
// vref : reference voltage[V,A]
// vspply_p : positive supply voltage [V,A]
// vspply_n : negative supply voltage[V,A]
//
//INSTANCE parameters
// gain=gain[]
// freq_unitygain=unity gain frequency[Hz]
// rin=input resitance[ohms]
// vin_offset=input offset voltage referred to negative[V]
// ibias=input current[A]
// iin_max=maximum current[A]
// rsrc=source resistance[A/F]
// rout=output resistance[Ohms]
// vsoft=soft output limiting value[V]
//
//
MODEL parameters
//{none}
//

module opamp(vout,vref,vin_p,vin_n,vspply_p,vspply_n);
input vref,vspply_p,vspply_n;
inout vout,vin_p,vin_n;
electrical vout,vref,vin_p,vin_n,vspply_p,vspply_n;
parameter real gain=835e3;
parameter real freq_unitygain=1e6;
parameter real rin=1e6;
parameter real vin_offset=0;
parameter real ibias=0;
parameter real iin_max=100e-6;
parameter real rsrc=0.5e6;
parameter real rout=80;
parameter real vsoft=0.5;
real c1;
real gm_nom;
real r1;
real vmax_in;
real vin_val;

electrical cout;

analog begin

@(initial step or initial_step("dc")) begin
c1=iin_max/(rsrc);
gm_nom=2*pi*frq_unitygain*c1;
r1=gain/gm_nom;
vmax_in=iin_max/gm_nom;
end

vin_val=V(vin_p,vin_n)+vin_offset;

//
///Input stage.
//
I(vin_p,vin_n)<+(V(vin_p,vin_n)+vin_offset)/rin;
I(vref,vin_p)<+ibias;
I(vref,vin_n)<+ibias;

//
//GM stage with slewing
//
I(vref,cout)<+V(vref,cout)/100e6;

if(vin_val>vmax_in)
I(vref,cout)<+iin_max;
else if(vin_val< -vmax_in)
I(vref,cout)<+-iin_max;
else
I(vref,cout)<+gm_nom*vin_val;

//
// Dominant Pole.
//
I(cout,vref)<+ddt(c1*V(cout,vref));
I(cout,vref)<+V(cout,vref)/r1;

//
//Soft Output Limiting.
//
if (V(vout)>(V(vspply_p)-vsoft))
I(cout,vref)<+gm_nom*(V(vout,vspply_p)+vsoft);
else if(V(vout)<(V(vspply_n)+vsoft))
I(cout,vref)<+gm_nom*(V(vout,vspply_n)-vsoft);
end
endmodule

during simulation
output is getting saturated
this is in-built code
i m dealing with macromodel so i m using it

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Geoffrey_Coram Senior Fellow Offline Posts: 1998 Massachusetts, USA	Re: problem in simulation Reply #5 - Oct 9^th, 2007, 9:48am You should try sanity checks like: tie both inputs to ground, make sure you get 0 out. Your VA code is missing the output stage that was shown in the original (non-VA) code. In your VA code, I see V(vout) being probed, but I don't see any contributions to vout, neither current nor voltage.
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raveendras4a5

New Member

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Posts: 4

Re: problem in simulation
Reply #6 - Feb 21^st, 2012, 8:43pm

Hi Geoffrey_coram,

I am also trying to Behaviorial Modeling of Op-Amp. I have simulated the above Code, I am getting output.

But, I didn't understand where is that "cout" node comes into picture. & I couldn't able to get exact behavioral mode diagram for the above code..

Actually I need to design the 2 input & 2 output differential Amplifier. So, How Can I modify the above code to get 2 differential Outputs.

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raveendras4a5 New Member Offline Posts: 4	Re: problem in simulation Reply #7 - Feb 21^st, 2012, 10:13pm Hi Rakeshkumar, Do you have the Behavioral model of the above program?? I tried to extract the behavioral view of this program but couldnot able to do that. If you know pls let me know too. Where did you get this programm.? At lrast tell me that one.
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boe Community Fellow Offline Posts: 615	Re: problem in simulation Reply #8 - Feb 23^rd, 2012, 8:37am Hi, It seems that in the Verilog-A version of the code the output stage is missing, which is included in the first HDL model. - B O E
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