This basically results that your Assura extract.rul did not recognized the way you draw your pins in the layout editor.

Is there a design manual for your design kit, which probably explains how to
draw the pins that Assura can recognize it?

It would help to know:
- On which database you run your LVS check on Cadence DFII or GDSII?
- How and with which layers do you usually draw your pins in the layout editor?
- How does your pin recognition section in the Assura extract.rul file look
 like?


My Assura code looks like follows:

;; Create labels form DFII pins
         m1_text      = pinText( "METAL1" )
     ...
;; Pin creation for GDSII
     m1_text        = textToPin( 131 type(  0 ) )

;; Establish/Extract connectivity section
geomConnect(
     ...
     label( m1_text m1 )
     ...
) ;; close geomConnect


This allows me to draw pins in the layout editor with the
'Create -> Pin' command on the metal layer of the interconnect
and realizes pins in GDSII if the interconnect has a label, which
can be added by 'Create -> Pin' as well.

There is also an old thread discussing this issue. http://www.designers-guide.org/Forum/YaBB.pl?num=1160022166

Bernd