Hi Ken, all,
I know this topic was already mentioned, but I do not think the answer was really exhaustive.
I'd like to see a step by step tutorial on how to simulate phase noise OR Jitter in a delay chain (a long inverter chain).
There are various articles I read on this topic but never a test case.
In one of ppt from Ken there are lot's of useful informations, but the risk to make a mistake is high.
1) when we measure peak noise were should we look, output of the current inverter being examinated, the next, one after the next until the highest peak is reached?...
2) supply noise is also there (probably one of the biggest contributor) how do we treat it? does it conunt only once for frequecies below the total delay and add in power for all inverters for frequecies above or close to each cell delay?
3) adding noise from individual inverter assuming each of those noise contributor indipendent isn't 100% if during the transistion the  2 or 3 following stages aren't fully switched.

What about this technique (using spectre and a lot of memory):
assume you want to calculate the jitter added to a 10MHz clk and the delay chain of few hundreds inverters is about 50ns, add an ideal 50ns delay and close it in a "ring" oscillator structure. Would the classical oscillator pnoise produce the right answer assuming we put enough sidebads to be in the order of the unit cell delay.
If this technique doesn't work than it means that any ring oscillator with a significant number or stages would not be correctly predicted by the pnoise.

any comment, link, book on this topic really is appreciated