I want to design a multi channel ADC chip by using the first order SDM.

The chip contains 16 channels and provides about 80dB dynamic range, 20Ksps datarate. In this application, the acquired signal will be processed in time domain. So the distortion of the ADC is of less importance.

Can this design is implemented by continuous time circuit with the over sampling frequence of 10MHz. And can higher dynamic range be gotten by using higher over sampling rate.

Are there any other constrains in such design.

Can some one give me a comprehensive guide on simulating the SDM on different level by using Cadence spectre.

Hi Michael.Yu

I agree with trashbox considerations. In addition and concerning your other questions...

1) To a first order using CT or SC modulators do not limit the DR (other secondary effects like CK feedthrough , charge injection, etc; migth limit the SNDR for the SC case). So you could use CT
2) Of course, by increasing the OSR you´ll get better SNR (or equivalently more DR)
3) You might want to consider second order modulators (if your app allows you to) to guarantee the 80dB required target.

As for modulator simulation, I would start by simulating the "behavioral" model for the system, preferably in Matlab. After you got the desired DR then you can create the same model (with ideal components) in Cadence and check for the same performance. Finally you can start incorporating real components into your model and keep checking for DR (obviously simulations will take longer and longer as you incorporate real components)

Hope this helps
Tosei