Dear all,
I've just read the paper/presentation from session 4.2 from BMAS 2007 (by Sabet & Riad).
They model the output voltage saturation/limiting of a general analog output stage as follows (see listing 1 in their paper):
Code:if Vin < Vlim1 then
Vx = Vlim1
else if Vin > Vlim2 then
Vx = Vlim2
else
Vx = Vin
Nothing is mentioned about potential problems/drawbacks using this approach.
I have however used this in my first attempts to model an OTA (for use in a SC filter) and I noticed this kind of model introduces a discontinuity which can (does) lead to severe simulator convergence issues. At that time, I was using Eldo.Therefore, I would suggest to introduce some kind of 'smoothing' instead of this hard clipping.
If you also experienced (simulation) problems with this kind of model, please comment.
Regards
Peter