Howdy

I am finishing work on a cml output path for a crystal oscillator.  Based on sourcelink and material from here, I designed a noiseless verilog limiter calibrated to the linear range of my logic gates to improve phase noise measurement accuracy.  Still, my block drives an edge triggered receiver which will never propagate noise contained in my falling edge transition, so I still need to find a way to render my falling edges noiseless if I am to produce an accurate simulation result predictive of actual noise propagation in my system.

Repeated attempts to realize a verilogA model which clips off noise outside the linear range of the receiver, and remove noise on falling edges, have only produced a compendium of error messages from Spectre, the verilogA code parser, et cetera.

Has anyone a suggestion about how to implement an extension to the noiseless AM filter to remopve falling edge noise?