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tm123

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Digital Sigma Delta for Fractional PLL
Nov 13^th, 2007, 7:51pm

Hello,

I am trying to design a sigma delta modulator for a fractional PLL. �I plan on using a 3rd order modulator, with multi-bit quantizer. �The architecture I would like to use is 'multiple feed forward', which seems to be common in fractional pll's. �The one thing I am not sure of is how to calculate the stable input range of the modulator. �Is it dependent on the number of bits in the quantizer, or the NTF, or both? �Is there good literature I can use to learn about this? �Thanks in advance.

Tim

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pancho_hideboo

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Re: Digital Sigma Delta for Fractional PLL
Reply #1 - Nov 13^th, 2007, 11:55pm

Quote:

I am trying to design a sigma delta modulator for a fractional PLL.
I plan on using a 3rd order modulator, with multi-bit quantizer.
The architecture I would like to use is 'multiple feed forward', which seems to be common in fractional pll's.
The one thing I am not sure of is how to calculate the stable input range of the modulator.
Is it dependent on the number of bits in the quantizer, or the NTF, or both?

If your multi-bit quantizer is more than 4bits, a stability is almost determined by NTF.

Quote:

Is there good literature I can use to learn about this? �Thanks in advance.

Following is a good book as introduction.
http://www.designers-guide.org/Books/#Schreier-2004

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tm123 Community Member Offline Posts: 67 Chicago, IL	Re: Digital Sigma Delta for Fractional PLL Reply #2 - Nov 14^th, 2007, 7:46am Thank you for your comments. I have the book 'Understanding Delta Sigma Data Converters' so I will take a look in there. I think the quantizer is going to be 7 bits. So can the stable input range be determined from plotting the poles/zeros of the NTF in the z plane? Thanks again. Tim
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tm123 Community Member Offline Posts: 67 Chicago, IL	Re: Digital Sigma Delta for Fractional PLL Reply #3 - Nov 16^th, 2007, 8:43am Sorry, I mistakenly said the quantizer would be 7 bits. It will be 3 bits for 7 levels. Tim
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