I built a gated pll for CDR in serdes.
Every block was implemented in verilog-a. And the structure is shown in Fig.1.

When the gated vco was disabled, everything is ok. The control voltage which is highlighted in Fig.1 is shown in Fig2.

At the moment when the gated vco was enabled while the pll locked, there is a bump in control voltage and the pll will be locked at another freq as shown in Fig3.

I just wonder What introduces this wield step in control voltage.
And I tried to use different method and different simulator this bump can not be eliminated.

Fig.3

and another thing ... maybe you should try to use a vcvs to couple the second oscillator to the control voltage. Maybe it's just some sort of current source problem coming from the CP/LF ?