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Verilog_A modeling (Read 3174 times)
qinshijie
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Verilog_A modeling
Nov 20th, 2007, 12:51am  
how to describe an module consisting of both analog submodules and digital submodules with Verilog_A language,or both Verilog_A and Verilog HDL language?
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ACWWong
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Re: Verilog_A modeling
Reply #1 - Nov 20th, 2007, 2:08am  
You should use verilogAMS.
Try this website to get started... http://www.designers-guide.org/VerilogAMS/
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qinshijie
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Re: Verilog_A modeling
Reply #2 - Nov 20th, 2007, 6:45pm  
thank you for your suggestion,ACWWang!
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