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The scale down factor (Read 2288 times)

jimwest Junior Member Offline Posts: 26	The scale down factor Nov 25^th, 2007, 11:17pm I'm preparing for a project proposal about Giga ethernet PHY. I have to estimate a area shrink factor, from the 0.13 to 65nm cmos process. I don't have the experience in 65nm, so could you guys give me some hits. Thanx!! B/R, Jim
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ACWWong

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Oxford, UK

Re: The scale down factor
Reply #1 - Nov 28^th, 2007, 3:41am

digital synthesized cell "should" reduce by factor 4 due to factor 2 reduction in channel length, but this might not be the case for your techonlogy due to the back-end (metals, vias etc.) not scaling effectively. A good way to estimate is to compare the area of a standard cell (e.g a NAND or flip-flip) between 0.13u and 65nm...
of course "analog" circuits won't shrink that much, especially if using spiral inductors or other passives...

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jimwest Junior Member Offline Posts: 26	Re: The scale down factor Reply #2 - Nov 28^th, 2007, 7:10pm Hi, If the area is not that directly related to the process for analog, then how about the power consumption? Suppose that case 1 the supply voltage doesn't change, how about the power consumption for the 65nm process? case 2 the supply voltage reduced, how about the power consumption for 65nm process? B/R, Jim
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