I m using TSMC .18um process, currently simulate on a POR, the threshold voltage is around 1.214V. As the output POR will go in to some logic gates (DFF and inverter), so it is important to know whether this Vthreshold is able to let the logic regconized as logic "high" or not. I found online that the VIH of CMOS 1.8V = 1.1V. I would like to ask is this value actually is just standard for all the standard cells? I tried to search in TSMC website, then in the document from TSMC named "artisan_tsmc18_stdcell_databook.pdf", but inside the document i only able to get those parameters such as caps value, setup time, hold time etc. of the gates but cannot find any info regarding to the VIH VIL.
Can anyone advice on this?
Thanks in advance