Hi, in GPS chips, there is a 2 bit ADC to digitize the IF output and give MAG&SIGN output to the baseband part.
Then I see in Zarlink datasheets a clock is used to synchronize the MAG & SGIN to latched to the rising edge of the clk.
But, they use a 5.714M clk to latch a 4.309M signal when in theory the digital output should faithfully track the original IF signal and have a certain duty cykle about 30%.
I think for sampling it is impossible.
So here how do the ADC work?
And how to test whether the ADC works well?
Thanks!

Hi Edward,

Do you mean that the sampling rate is 4.309MHz?


Yawei