Terence
Junior Member
![* *](https://designers-guide.org/forum/Templates/Forum/default/starblue.gif)
Offline
![](https://designers-guide.org/forum/avatars/smiley.gif)
CAD Lab.
Posts: 23
Taiwan, R.O.C.
|
How should I expect the gate-capacitance to behave? ==> the capacitance will be similar to Cox once you operate the nMOS in accumulation mode.
Will it be significantly different from a native Nfet (for which I have a model) or a standard Nfet whose Vth is hand-edited to zero? ==> I suggest to check foundry's document. One more question. Supposing I raise the voltage of the structure's nwell to Vdd rather than its normal Vss tie. What happens to the gate capacitance in this configuration? ==> that will make the nMOS to operate at accumulation mode once you tie the gate to Vss. The capacitance will be close to Cox.
|