Dear all,

I want to design a LDO (0.18 um CMOS) and its spec is listed blow:

1. high PSR in wide band (PSR 60 dB, from DC to 1M);
2. output voltage is about 1.5V from vdd of 2.8V;
3. noise requirement: 30 nV/sqrt(Hz) @1 kHz

Is there any paper on this design issue you guys can suggest, or would you like to give me some design guidelines?

Thanks

Regards

Jason