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dpx4086

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why some layers missed in the extracted view ?
Jan 09^th, 2008, 11:55pm

why some layers missed in the extracted view ?
i put a MOS with it's d and s connected to ground, then layout, drc, lvs, and finally extracted.
but some layers missed in the extracted view of av_extracted, such as the poly layer.
i attached those snapshots in this post.
at the same time, i found some message unusual in CIW when it loading tech rule set file as i start the RCX :
......
\o *Info* Ignoring overWriteRuleSets from the State File
\o *Info* Ignoring selectedRuleSets from the State File
\o *Info* Ignoring selectedDirs from the State File
\o *info* Netlisting Option Virtual Metal Fill can take only "Shape"
\o *info* as a valid value when RCXFS is Enabled.
\o *info* Limiting Virtual Metal Fill value to "Fine Shape"
\o *info* Your RCX Setup Value for Virtual Metal Fill will be ignored.
\o *Info* Ignoring rcxNets from the State File
\o *Info* Ignoring rcxNetsFromFile from the State File
\o *Info* Ignoring rcxNetsFile from the State File
\o *Info* Ignoring rcxFSNets from the State File
\o *Info* Ignoring rcxFSNetsFromFile from the State File
\o *Info* Ignoring rcxFSNetsFile from the State File
\o *Info* Ignoring fixedNets from the State File
\o *Info* Ignoring fixedNetsFromFile from the State File
\o *Info* Ignoring fixedNetsFile from the State File
\o *Info* Ignoring inductanceNets from the State File
\o *Info* Ignoring inductanceNetsFromFile from the State File
\o *Info* Ignoring inductanceNetsFile from the State File
\o Load complete.

could any body tell me how to solve this problem ???
i'm using the ic5141usr1 and the assura 314 with chrt 0.18 process.
thank you soooooo much !!!

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Schematic-1.png

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dpx4086 Junior Member Offline Posts: 15	here is the layout Reply #1 - Jan 9^th, 2008, 11:57pm here is the layout
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dpx4086 Junior Member Offline Posts: 15	here is the av_extracted Reply #2 - Jan 9^th, 2008, 11:59pm here is the av_extracted
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bernd

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Munich/Germany

Re: why some layers missed in the extracted view ?
Reply #3 - Jan 10^th, 2008, 12:33am

In Brief, the extracted view is just a representation of your layout
view with device, parameter and connectivity information plus parasitic
devices if desired, that it can be netlisted and simulated.

In the command rule file it's defined how much layers will be copied over
from the layout to the extracted view. Usually this are just the layers
which are used for the interconnects and they will have the layer purpose
'net'. This is enough to probe signals in the extracted view.

But this depends on your design kit and the people who are developing it.

Bernd

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dpx4086

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Re: why some layers missed in the extracted view ?
Reply #4 - Jan 13^th, 2008, 7:04pm

bernd wrote on Jan 10^th, 2008, 12:33am:

In Brief, the extracted view is just a representation of your layout
view with device, parameter and connectivity information plus parasitic
devices if desired, that it can be netlisted and simulated.

In the command rule file it's defined how much layers will be copied over
from the layout to the extracted view. Usually this are just the layers
which are used for the interconnects and they will have the layer purpose
'net'. This is enough to probe signals in the extracted view.

But this depends on your design kit and the people who are developing it.

Bernd

thanks for your reply,Bernd.
when i extracted a capacitor , there is no layer left , but a parasitic capacitor symbol. that means the layout circuit was cut off in the place of capacitor.
and even more, i made the post simulation using the extracted circuit , the results were totally different to pre-layout simulation results.

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didac

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manresa,spain

Re: why some layers missed in the extracted view ?
Reply #5 - Jan 15^th, 2008, 12:02pm

Hi dpx4086,
Have you checked if this "parasitic capacitor" is the real capacitor?I've worked with PDK's that make exactly this thing on the extracted view of the capacitors-erase all layers an put a capacitor symbol in it's place-. About your simulation results after extraction you can do a sanity check extracting without parasitics and see if the extracted simulation match, then add R,then add C parasitics and you can view the degradation due to parasitics.
Hope it helps,

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dpx4086

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Posts: 15

Re: why some layers missed in the extracted view ?
Reply #6 - Jan 16^th, 2008, 5:05am

didac wrote on Jan 15^th, 2008, 12:02pm:

Hi dpx4086,
Have you checked if this "parasitic capacitor" is the real capacitor?I've worked with PDK's that make exactly this thing on the extracted view of the capacitors-erase all layers an put a capacitor symbol in it's place-. About your simulation results after extraction you can do a sanity check extracting without parasitics and see if the extracted simulation match, then add R,then add C parasitics and you can view the degradation due to parasitics.
Hope it helps,

thank you for your reply,didac.
but how to make "sanity check extracting without parasitics" ?
i tried to look for this in the help of assura, but no thing found.
would you plz post this in detail. thx.

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