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QVCO mismatch (Read 2033 times)
yhq0413
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QVCO mismatch
Jan 13th, 2008, 8:54pm  
I am designing a 4G QVCO.
The phase error is simulated with PSS.
schematic simulation result shows 0 90.1 180.3 270.5
then the simulation is performed on extracted layout netlist that includes the  parasitic resistance and capacitance,the result shows 0 90 185 275
how can I modify the layout?
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neoflash
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Re: QVCO mismatch
Reply #1 - Jan 19th, 2008, 7:00am  
From schematic level simulation, you should not see any mismatch. You can increase settling time delay setting.

From layout level simulation, I still suggest use transient to see the results. Then judge your next move.
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