Hi all,

Is the following statement true considering a spice like simulator (Cadenc spectre actually)

If I add a 1us clock source using an ideal voltage source in a design, which is pretty fast (takes say around
200us of time step without the clock source) the simulation time step becomes smaller and cannot go above
1us. This is because of the clock source.

Rajdeep

Hi stefan,

No no I do not want to increase my simulation speed up in this way, rather I have to add a clock and I find the simulation time is increasing due to this. This was expected!! But what I could not understand that the simulator takes steps greater than 1us!! How is it possible if I have a clock continously ticking at 1us, and not only that (possibly due to this) when I plot the clock waveform it is not showing a perfect 1us clock!!! rather at many places...like the following...
[img][/img]

As you can see after sometime the clock waveform is wrong. Infact the simualtion time step suddenly starts to become more. The clock was generated by using an ideal pulse type voltage source from analogLib.

Rajdeep

Rajdeep,

This is surprising and not the correct behavior. What version of Spectre are you using ? Can you reproduce the problem in a simple netlist ?

Thanks,
 John

Generally this occurs when there is a very large voltage else where in the circuit, perhaps because of of some idealized behavioral models in the circuit. Try setting the transient option relref to alllocal.

-Ken