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Mauricio Pardo New Member Offline Posts: 4 Atlanta, GA	PLL open loop simulation with Phase Models Jan 15^th, 2008, 7:38pm Hi, Can anyone give me some advice about how to simulate an open loop PLL (i.e. without closing the VCO output with the corresponding PFD input) without receiving the error message "Zero diagonal found in Jacobian at..."? I need to know the phase noise performance of a possible mirror of the VCO. Thanks, Mauricio.
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Eugene

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Re: PLL open loop simulation with Phase Models
Reply #1 - Jan 15^th, 2008, 10:34pm

If you are using a phase domain model you have at least one free integration in your loop. Thus, when you open the loop you are trying to do a DC analysis of a free integration, which of course blows up at DC. You can tame the free integration at DC by placing an initial condition on it but I THINK that also removes the integration from your AC and noise analyses. I would try using VerilogA for the free integration and then exploiting a cool feature of VerilogA that lets you do different things for different analyses. You can write an "if" statement that bypasses the integration during DC analysis but then includes it for AC and noise analyses.

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Mauricio Pardo

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Re: PLL open loop simulation with Phase Models
Reply #2 - Jan 16^th, 2008, 2:40pm

Thanks for your response Eugene...

However, I'm new in all the Verilog-A stuff, and I don't know exactly how to bypass the DC analysis. A lot of things come now to my mind... First, the simulator runs a DC analysis although I only select AC analysis? How can be the clause for the if statement (if V = 0)?

I really appreciate if you can guide a lit bit more...

Thanks again for your reply.

Mauricio

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Eugene Senior Member Offline Posts: 262	Re: PLL open loop simulation with Phase Models Reply #3 - Jan 16^th, 2008, 7:35pm There's an example of the"if" statement in the state_space_ave_pfd model in Cadence's pllLib. The path to the pllLib is ...dfII/samples/artist/pllLib
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jimwest

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Re: PLL open loop simulation with Phase Models
Reply #4 - Feb 21^st, 2008, 11:48pm

Eugene wrote on Jan 15^th, 2008, 10:34pm:

If you are using a phase domain model you have at least one free integration in your loop. Thus, when you open the loop you are trying to do a DC analysis of a free integration, which of course blows up at DC. You can tame the free integration at DC by placing an initial condition on it but I THINK that also removes the integration from your AC and noise analyses. I would try using VerilogA for the free integration and then exploiting a cool feature of VerilogA that lets you do different things for different analyses. You can write an "if" statement that bypasses the integration during DC analysis but then includes it for AC and noise analyses.

To Eugene,
I'm quite confused how to evaluate a pll with its phase domain model by DC and AC simulation.
Maybe AC can be used as trans in phase domain. But which parameter can we get by DC analysis?

Thanx.

Jim

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Ken Kundert Global Moderator Offline Posts: 2386 Silicon Valley	Re: PLL open loop simulation with Phase Models Reply #5 - Feb 22^nd, 2008, 12:52am Perhaps we can go back to the beginning. I see no reason why you are getting a zero diagonal in the Jacobian. Perhaps you can describe more about this situation. Spectre generally tells you where in the circuit the 0 was detected, what did it finger? -Ken
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Mauricio Pardo

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Atlanta, GA

Re: PLL open loop simulation with Phase Models
Reply #6 - Feb 22^nd, 2008, 5:41am

Hi everyone...

All the situation appeared when I disconnected the feedback loop in the PLL (from the VCO to the PFD). What I was trying to do was trying to plot the phase noise of the VCO only to keep the plot in the Waveform Window and then plot the response of the PLL (restoring the feedback connection). Thus, when I try to run the AC and Noise analysis for the first situation, I obtained the message about the zero en the matrix, and the message was indicating the instance of the VCO and also reported the idt0.

Therefore, I conclude that the integration of the VCO was the responsible for the error... To have my plot as reference, what I dit was to "comment" that statement in the Verilog model.

However, trying with different PLL configurations, once I while the error appears again limiting some of my ideas about alternative PLL configurations. Hence, my question is more directed in the "resulting noise transfer function plot" that an alternative configuration can configurate... I think that the "comment" strategy does not work here because without the idt statement the loop is broken...

Is there any possible way to remove this situation? Is the error a notice that the PLL configuration that I am trying is weird or impossible to construct?

Thanks to everyone!

Mauricio.

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Ken Kundert Global Moderator Offline Posts: 2386 Silicon Valley	Re: PLL open loop simulation with Phase Models Reply #7 - Feb 22^nd, 2008, 11:50am Are you using behavioral models or transistors? -Ken
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Mauricio Pardo New Member Offline Posts: 4 Atlanta, GA	Re: PLL open loop simulation with Phase Models Reply #8 - Feb 22^nd, 2008, 11:56am Hi Ken, I am using the behavioral models in Verilog-A. I followed your paper in how to extract the noise characteristics. Mauricio.
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Ken Kundert Global Moderator Offline Posts: 2386 Silicon Valley	Re: PLL open loop simulation with Phase Models Reply #9 - Feb 22^nd, 2008, 12:46pm The problem is that the phase is undefined. You will need some feedback to make this work. -Ken
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