Stefan wrote on Jan 27th, 2008, 2:16am:verilog misses some extensions (like wreal data-types) that would be crucial for jitter simulations.
However you can implement an oscillator with jitter using $dist_normal (don't know exactly if this is available in pure verilog).
Thank you very much for your reply. Now I am sure that $dist_normal is the syntax in verilog-A, not in pure verilog.
Could you tell me know whether can simulate jitter by verilog-A or not? And how can I download software that helps to simulate like Model Sim? Because I'd like to simulate following code.
Thank you very much
Here is code that I found:
// Fixed frequency oscillator with white accumulating jitter.
//
// Accumulating jitter is the jitter associated with a free-running oscillator.
//
module osc2 (out);
output out; voltage out; // output signal
parameter real freq=1 from (0:inf); // output frequency
parameter real vl=-1; // high output voltage
parameter real vh=1; // low output voltage
parameter real tt=0.01/freq from (0:inf); // transition time of output
parameter real jitter=0 from [0:0.1/freq); // white period jitter
integer n, seed;
real next, dT;
analog begin
@(initial_step) begin
seed = 286;
next = 0.5/freq + $abstime;
end
@(timer(next)) begin
n = !n;
dT = jitter*$rdist_normal(seed,0,1);
next = next + 0.5/freq + `M_SQRT1_2*dT;
end
V(out) <+ transition(n ? vh : vl, 0, tt);
end
endmodule
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Is it able to Simulate jitter by verilog-HDL? (Read 6827 times)