Berti
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Hi,
the non-overlap time should not be to large because you want as much time for settling as possible. But on the other hand it should be large enough that the clocks never overlap (taking into account jitter, skew rise-fall time mismatch etc.). An overlapping clock will destroy the performance.
But since 12.5MHz is relatively slow, I think you can choose a reasonably high non-overlap time (e.g. 0.5ns, this but also depends on you technology, and rise-fall times of clocks).
Circuit implementation for non-overlapping clock generators you can find in a textbook about DSM (e.g. Schreier)
Good luck, regards
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