Visjnoe
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Dear all,
Imagine there's a 'classic' PLL (3-state PFD/CP, LC oscillator, integer N diivder) which locks nicely. Let's assume the Kvco of the LC oscillator equals +100MHz/V, meaning the VCO frequency and the VCO tune voltage are related by a positive derivative (~when the tune voltage increases, the VCO frequency will also increase).
Now assume I leave the whole PLL the same, but negate Kvco to -100MHz/V, meaning that now the VCO frequency will decrease when the tune voltage increases.
My question now is: would the PLL still lock? I would say no, since when e.g. the PFD/CP is giving 'UP' pulses to increases the VCO output frequency, the PLL will now actually do the opposite, namely lowering the VCO frequency.
Therefore, I would say the PLL is unstable and will divert to a condition where the LF voltage is clamped to one of the supply rails.
The problem now is however that I have a nearly-ideal Simulink model which proofs me wrong (PLL still locks when I negate the VCO gain).
Does anyone have any comments on this?
Kind Regards
Peter
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