This Verilog-A module sets the output voltage to a random value at each Newton iteration during transient timestep integration. This will cause non-convergence.
If you need a white (or colored) noise source with a given bandwidth, you will need to know (but don't know inside Verilog-A):
i) transient integration method (trap, euler, gear, etc.)
ii) transient timesteps
iii) perform transient timestep error control for a system of noisy circuit equations
To model a white noise source, simply run transient noise, and call the $white_noise(..) function in Verilog-A or equivalent in your circuit simulator.
Behavioral noise models take tender loving care to create and it is difficult to check for their accuracy because interesting noise processes in ADCs, PLLs and oscillator transients are time-varying and correlated over time (with memory effects).
You are generally better off running transient noise (or periodic noise, when applicable) on the transistor-level netlist.
Geoffrey_Coram wrote on Apr 23rd, 2008, 6:12am:I guess you didn't understand my suggestion about Verilog-A $rdist_normal. This module generates new a new random value each time it is called. The trick is getting a circuit with this to converge, and deciding how often it needs to be called to accurately represent white noise of a given bandwidth.
Code:`include "disciplines.vams"
module randomv(out);
inout out;
electrical out;
parameter real mean = 0;
parameter real stddev = 1 from (0:inf);
integer seed;
analog begin
@(initial_step) seed = 1;
V(out) <+ $rdist_normal(seed, mean, stddev);
end
endmodule
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