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analoghua

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current-steering digital-to-analog converter
Mar 05^th, 2008, 8:06pm

hello, I have a question regarding the design of a current-steering digital-to-analog converter. It seems that the main errors are static error due to unit current element mismatch (in a multi-bit case) and dynamic error due to asymmetric switching of control signals. But a unit current element seems also to have varying current flow due to the varying voltage of the node which the unit current element is connected to? How can we minimize the dependence of the current on the node voltage if we are limited to three transistors in series including the switching transistor due to tehcnology/voltage limit? What is a good way to size them?

For a single-bit current-steering DAC, how do we compute the noise power due to this effect? Do we have to know the statistics of the node voltage to compute the noise power? also the statistics of the input?

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solidstate

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Munich, Germany

Re: current-steering digital-to-analog converter
Reply #1 - Mar 6^th, 2008, 8:10am

To answer some questions in your first paragraph: first of all, the current mirror should be as long as possible, to make the effect of channel length modulation as small as possible to begin with. If you then use a cascode transistor on top of the mirror, you reduce the voltage swing at the drain by the voltage gain of the cascode, further reducing this error. If the error is still too big in this way (or if you want to widen your design space for the L of the current mirror), you can gain-boost that cascode, further fixing the drain voltage of the mirror.

If untreated, this effect is not noise, but nonlinearity. I'm not sure what you are referring to in the second paragraph.

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loose-electron

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Re: current-steering digital-to-analog converter
Reply #2 - Mar 14^th, 2008, 10:31pm

Beg to differ -

Cascode current source will keep the Vds of the current source transistor (bottom one in an NMOS cascode) the same (to a first order) and the primary consideration on that transistor is matching of current sources. The cascode transistor (top in the NMOS cascode) is generally at minimum length because it does not effect the current value, and you want the transconductance as high as possible.

solidstate wrote on Mar 6^th, 2008, 8:10am:

To answer some questions in your first paragraph: first of all, the current mirror should be as long as possible, to make the effect of channel length modulation as small as possible to begin with. If you then use a cascode transistor on top of the mirror, you reduce the voltage swing at the drain by the voltage gain of the cascode, further reducing this error. If the error is still too big in this way (or if you want to widen your design space for the L of the current mirror), you can gain-boost that cascode, further fixing the drain voltage of the mirror.

If untreated, this effect is not noise, but nonlinearity. I'm not sure what you are referring to in the second paragraph.

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Jerry Twomey
www.effectiveelectrons.com
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