Hi all,

I am new to verilog-A simulation of pll. When I read Ken's "Predicting the phase noise and jitter of pll-based frequency synthesizers", in the VCO model

Theta(out)<+2*'M_PI*gain*idt(V(in))

So here the Theta(out) will increase infinitely unless V(in) is zero,  then small signal simulatoin doesnot work, how can I solve this problem?

Another question is, I converted all the simulated block phase noise (dBc/Hz) into "power" by 10^(L/10) and then input them into noise table, is that the right way to do it?

Thanks a lot
chenyan

Thanks a lot! pancho_hideboo.

Yes, I think idtmod will work, but we have to do pss+pnoise right? And we will use again 2 frequencies, one reference and one vco.

But Ken mentioned with phase domain models, using only small signal simulation like AC or noise will do. Would there be an alternative way to do so?