neoflash wrote on Apr 2nd, 2008, 7:39am:It finally comes. Process scaling is so aggressive that designing a simple op-amp becomes so hard.
In 45nm process, Vth of transistor is as high as 450mV-500mV while the voltage supply is as low as 0.95v. Any good idea to design a rail-rail OTA in this kind of process?
sounds like fun... I can't remember all of the dates/authors, but...
back gate input (see Kinget's work)
floating gate in series with input pair (Hassler/Georgi Tech may be a good start)
charge pump up the source/gate of tail current source (JSSC article)
"natural/native" NMOS (0 Vt)... ISSCC
Cap level shifting (Gieger's CICC stuff ~2003)
Use inverting configurations so the input common mode is constant. This is the best performing config.
long time ago I did a SC circuit that sampled the Vgs of the input pair devices during the first phase (just switch both caps to the tail current source, while having the other ends connected to the input gates), and then put them in series with the gate during the second phase. This made the opamp rail/rail with canceled offset.