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kiran123

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Re: Design of Rail-Rail OTA in 45nm Process
Reply #15 - Apr 20^th, 2008, 9:47pm

neoflash wrote on Apr 18^th, 2008, 6:54am:

loose-electron wrote on Apr 17^th, 2008, 3:16pm:

Input rail to rail design is typically down with a PMOS differential pair and an NMOS differential pair structure -

Each has its own current source, and each has its own "current mirror diode" active load.

The second gain stage of each device mirrors out as a current, and then the signals from the two structures are summed together, and used to drive the output driver.

The concept is roughly illustrated in the attached picture. Although this implementation uses diode connected loads, but the general idea is shown.

Doing this design in 45nm becomes extremely difficult...

Hi Neoflash,
i am not going to do it in 45 nm , what i want from you guys is exact schematic architecture & its design techiniques ( if you have any docs) used to create Input Rail to Rail ampamp that's it

Regards
Kiran

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Berti

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Re: Design of Rail-Rail OTA in 45nm Process
Reply #16 - Apr 21^st, 2008, 12:07am

Hi Kiran,

I think people got that. But this discussion initially started with OTA design in 45nm and I think we should
come back to that (very interesting) topic since it will affect most of us analog designers (sooner or later).

Your question on the other hand is very specific ... and unfortunately I have never designed a rail-to-rail input
stage.

Regards

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RobG

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Bozeman, MT

Re: Design of Rail-Rail OTA in 45nm Process
Reply #17 - Apr 21^st, 2008, 1:36am

neoflash wrote on Apr 2^nd, 2008, 7:39am:

It finally comes. Process scaling is so aggressive that designing a simple op-amp becomes so hard.

In 45nm process, Vth of transistor is as high as 450mV-500mV while the voltage supply is as low as 0.95v. Any good idea to design a rail-rail OTA in this kind of process?

sounds like fun... I can't remember all of the dates/authors, but...
back gate input (see Kinget's work)
floating gate in series with input pair (Hassler/Georgi Tech may be a good start)
charge pump up the source/gate of tail current source (JSSC article)
"natural/native" NMOS (0 Vt)... ISSCC
Cap level shifting (Gieger's CICC stuff ~2003)

Use inverting configurations so the input common mode is constant. This is the best performing config.

long time ago I did a SC circuit that sampled the Vgs of the input pair devices during the first phase (just switch both caps to the tail current source, while having the other ends connected to the input gates), and then put them in series with the gate during the second phase. This made the opamp rail/rail with canceled offset.

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neoflash Community Fellow Offline Mixed-Signal Designer Posts: 397	Re: Design of Rail-Rail OTA in 45nm Process Reply #18 - Apr 21^st, 2008, 6:02am Berti wrote on Apr 20^th, 2008, 10:18am: Hi Neoflash, Would you please comment why you think that this structure might be difficult to realize in 45nm. Regards diode connected load device will consume too much voltage head room, thus input transistor pair easily enter triode region.
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