Gines
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Posts: 2
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Hi friends,
I am a beginner RF designer and I have implemented a PLL frequency synthesizer at 2.5GHz with a 2.5MHz clock reference and 30kHz loop bandwidth. During testing I have detected a great number of spurs within the whole bandwidth of interest from 30kHz up to 10MHz offset from the carrier. Although references harmonics at multiples of 2.5MHz are no-significant, the spur amplitudes are always about 20dB over the phase noise floor.
The justification of this behaviour is out of my knowledge. In this sense, I wonder,
1.- Could these spurs be caused by the non-idealities of the charge-pump (output resistance, mismatching,…) or the integer frequency divider (8/9 prescaler, 120-program counter and 5-bit swallow counter)?. If this is the case, is there any simulation method or analytical procedure to predict such behaviour?. I have revised the literature but I have not found any solution.
2.- Could the test setup produce these effects?
Thank you very much in advance. Gines
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