Hi,
A capacitance loading this kind of dividers could be a real problem, you must codesign a buffer to isolate the divider from the load(with a small transistor as the input of this buffer to avoid this loading). Also in the layout you must pay attention to the parasitics of the output lines(believe me I expended 4 hours optimizing the outputs of one of this dividers at layout level).
About that a tiny input makes the divider work it's not strange at all, I recommend that you do a 2-D parametric with the input signal(Vin and fin), if you plot like a contour with Matlab you will see the two operating regions(free running and locked divider) and you will also see how depending on the input frequency more or less input level is needed for the divider to work(you can also see if your frequency it's too close to the limit where the divider will stop working).
Hope it helps,
PS:it's compulsory the use of a master-slave divider?,maybe it's worth the effort to see at an Injection Locking frequency divider(the problem it's the area overhead...)

Hi,

Is your dividers CMOS divider or SCL/ECL dividers?  Do you mean you are designing a divide-by-4 divider?

Hm... I found that it is more tedious to design dividers without static timing analysis especially in large synchronous divider that has many functional options at high frequency. I have to manually look for the timing margin from simulation result for all the flops in the circuits.

You mentioned that your circuit will not work when you attached a 5fF capacitors as your load so it seems to me you have a synchronous design. If timing, noise and power is not an issue, I would suggest simpler design that is asynchronous i.e. cascade 2 simple and identical divide-by-2 together so that optimization and functional check is main on the first critical divider. The 2nd divider will most likely to work at lower frequency and it also serve as a buffer that decouple your critical first divider from your load. That will certainly reduce your risk and shorten the design time.

We have a large synchronous design before and we really have a tough time to ensure it is fully-functional. As mentioned by didac, layout optimization is really crucial.

Hope that helps.

Regards,
Chase