Hi Monkeybad,

First, I don't think a duty cycle corrector must increase jitter significantly. At least the additional jitter is not larger than a divide-by-2.  
Second, a 2X frequency VCO + divide-by-2 doesn't mean 2X times power logically. For eg. a VCO make of N CMOS inverter, say INVX1, runs at 1X frequency while a VCO made of 2N CMOS inverters (INVX1) runs at 2X freuquency. They consume the same power because the inverters toggle 2N times in the period 1/(2X frequency).  Intuitively, that is due to the inverter does not consume static power. If a VCO is made of the delay cell with static current, say a differential buffer. Assume all the differential buffers are of the save size and the same delay time, a 2X frequency VCO made of the differential buffers consume half the power of 1X frequency VCO because a 2X frequency VCO has half quantity of the 1X frequency VCO.  
Third, it is complicated to choose between 2X VCO and 1X VCO. The decision depends on the jitter requirement and other specific design requirement.

Best regards,
Yawei

Hi,

I agree with Yawei that it is very complicated to choose between 2X VCO and 1X VCO. In RF application, the VCO frequency is carefully planned to mitigate spurs and inteference. The requirement of having a DCC or divider often comes as the result of the frequency planning and the jitter performance of the VCO at the frequency of interest.

Some DCC are considerably low noise, i.e. they introduce noise that is not much more than a simple buffer depends on the overall design of the PLL and DCC. However, a divide-by-2 normally gives better 50% duty cycle than DCC as far as i know.

Regards,
Chase

both methods work.
DCC tends to be used more when power consumption is the most important
div-2 tends to be used more in RF design where duty cycle in a mixer is critical.