mus
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Hello everybody, Thank you in advance at which can help me to model in Verilog-A a counter. In fact I need a binary-coded Verilog-A just for a test bench of my circuit. The specifications which meet this binary are: 1. A single input for counting the pulses 2. Multichannel 8-bit (ouput 8-bits) 3. With a reset active on the low level. 4. After its maximum value (255) it takes the value 0 (ie modulo 256) Just for your information I have modelled the counter before relying on scales the flip flop D, JK, T modelled on Verilog-A. The counter modeled in this way works well, but I wonder is there a simpler way for to model it, as in the case of VHDL and Verilog.
Thank you very much, best regards
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