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problems for a mos transistor modeled in vhdl-ams (Read 3257 times)

alinalin19832007

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roman

problems for a mos transistor modeled in vhdl-ams
May 24^th, 2008, 2:48pm

Im trying to simulate an transistor that is modeled in vhdl-ams in Cadence environment IUS 5.7. The problems is that this model works fine IUS5.5 but in IUS5.7 i have some oscilations in the moment I try to switch off.
Can explain anybody why is this thing ?
What are the difference between two IUS?

thank y very much
I hope u understand what i want to say? ;)

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Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA	Re: problems for a mos transistor modeled in vhdl- Reply #1 - May 27^th, 2008, 5:27am Could be you're just getting lucky with one IUS. What does the capacitance model look like? Is it (correctly) formulated in terms of charge instead of capacitance * voltage? What happens to the channel charge when the device is suddenly turned off?
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alinalin19832007 New Member Offline Posts: 9 roman	Re: problems for a mos transistor modeled in vhdl- Reply #2 - May 29^th, 2008, 1:09pm The model works fine vgs<vds+3V , i dont know why is that
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