joel wrote on Jun 17th, 2008, 5:01pm:For loop bandwidth, modulate your reference clock at some frequency, and measure the corresponding output frequency modulation. Sweep the modulation frequency. When the normalized output frequency modulation amplitude is down by 3dB relative to normalized input modulation amplitude, you've got your 3dB loop bandwidth. Basically when you can see it start to attenuate, you're roughly at the loop bandwidth.
By the way, I've had good luck using Evercad Adit for PLLs because it has a retriggering measure statement. E.g. For each posedge, measure the time till the next. Do any other circuit simulators have this? I'm not aware if it in hspice or hsim, but they're constantly adding freatures. Cheers! /jd
Thanks, joel
I have done the simulation like your method a few days ago. But it is very slow. Do you have any better method?
What't your mean about retriggering measure statement? Do you mean that it can measure at every edge with one measure command?
It seems has no this feature in HSPIECE as I know.