Hi all,

if you take a transistor is saturation, the g_m is approximated as,

2I_DS/(V_gs-V_T)

and in subthreshold it is approximately

I_DS/nV_t

For the input referred channel noise in the saturation region we have,

V_n²=4kTγ/g_m = 2kTγ(V_gs-V_T)/I_DS

and in subthreshold,

V_n²=2kTn/g_m = 2kT(n²)V_t/I_DS

From these equations, it seems that subthreshold biasing offers better g_m per I_DS, better noise per I_DS, and comparable noise per g_m. Only drawback is subthreshold has higher input capacitance per g_m (resulting in lower f_T). Just want to double check if these manipulations seem strange to anyone?

BTW i understand the difficulty in defining V_T, however, i'm trying to confirm that weak-inversion (in between subthreshold and saturation) is basically the best biasing point. I also understand that linearity is poorer in weak-inversion/subthreshold...

thanks,
Aaron

Hi,
I agree with the deductions but I think that the effect of induced gate noise should be taken into account, I remember looking some papers about noise in high frequency transistors where the effect of induced gate noise in subthreshold caused a sharp increase in NFmin so I don't know if it holds the deduction about Noise.
PD:I will try to search the reference about noise in subthreshold...it must be somewhere on my PC...

Hi Aaron,
I've found the following reference:http://ieeexplore.ieee.org/iel5/8611/27289/01213917.pdf, I remember finding similar conclusions on another more recent paper, let me see if I can find it.
Hope it helps,

thanks,


the second paper looks quite interesting anyway. I'll read it later.

I read the first paper but there was something that didn't seem right. In page 2 column 1, paragraph 1, the author says that in the Van der Ziel Model, induced gate noise is inversely proportional to gm while the channel noise is proportional to gm. therefore gate noise will dominate when gm is low.

however, gate noise is referred to the gate while channel noise is referred to the channel. If we refer both noise sources to the gate, then both are inversely proportional to gm so channel noise will still dominate. This makes more sense to me since the way i understand it, this gate noise is actually due to the equivalent resistance formed because the bottom plate of Cgs/Cgd is connected to the channel...

Correct me if i'm wrong

thanks,
Aaron

aaron_do wrote on Jun 27^th, 2008, 5:26am:


Hi Aaron,

Tsividis is a reliable reference, but I am not sure about most simulation models. It would be good if you could find out how well the subthreshold region and noise are modelled in your process. Normally, good analog/RF processes have reliable models, but you never know.

One good check would be to see if the Gm varies smoothly as you sweep the current down.

You don't want to worry about "model noise".

Regards
Vivek

Hi,
I've checked the book "Design of Analog CMOS Integrated Circuits" by profesor Razavi and in the section of noise points that in presence of finite input impedance modelling the two-port with just a equivalent voltage noise source at the input it's incorrect(page 220) but I think that stills ignores contribution from induced gate noise(maybe I skipped something) in the book "The Design of CMOS RFIC" bt prof. LEE in the chapter of LNA design before the derivation of power constrain design method he derives the two-port representation of the MOSFET taking into account the induced gate noise.

So I think that in the end is the old issue that up to which frequency(or situation) you can make some assumptions.

PD:if you are interested just as historical curiosity I think that it could be interesting to see:"Theory of Noisy Fourpoles",H. ROTHEt, SENIOR MEMBER, IRE, AND W. DAHLKEt,Proceedings of the IRE,1956

Hi,
Good to know, it's a shame that I can't simulate this things with my PDK....
Just as curiosity did you end up seeing something similar to the reference about noise(i.e a sharp increase in noise and then saturation of the noise)?
Thanks,