Hi Aaron,

If you have really checked all process, supply voltage, temperature, bias current corners, then you should be ok in principle.

However, about the W/L deviation, did you consider the body effect in the diode-connected transistors? This coupled with your drain current (I am guessing it is very small), and input common-mode voltage (probably too low) might be the reason. I expect that you will have relatively lower speed due to the additional input cap, and higher noise due to the choice of gain and load, but I think you already have accounted for this.

You mention diode-connected NMOS loads. That would mean you are tying the drain and gate both to the top and to VDD. Is that correct? Normally, it is not advised to connect the gate directly to supply (reliability reasons).

Regards
Vivek

Hi Berti,

That was a little off the main topic. But what I get to hear all the time from people working on process tech is that the gate has a high chance of getting damaged, or atleast of getting its properties modified sufficiently to degrade performance when tied to VDD or VSS directly.

One reason appears to be antenna effect from the processing which is worse since VDD/VSS are usually the largest lines on chip, but which is reduced due to the many diodes. The other is that the VDD/VSS typically experience a large enough transient under ESD stresses that can degrade the gate, since the ESD protection clamps can only limit the voltage to a value a little beyond the rated limits.

Regards
Vivek

Hi mists,

Now we are really off the main topic. So I will just summarize what we get as "RULES" from our process guys.

1. MIM, PIP, MOSCAP all are fine as bypass caps but may not be tied directly to a supply pin. I am not sure if they forbid tying it directly to any external pin at all. All this is to prevent damage to these thin oxides.

2. As a solution, we are allowed to put a small series resistor (a few 100 Ohms), and a diode, basically primary ESD protection before connecting these to external pins. Alternatively, we have some dedicated supply bypass cells realized with MOS devices where the gain does not touch the external nodes. These have comparable cap, and are usually also used as FILL cells in digital libraries. I cannot post a schematic of course.

3. I do not know if the rules as given to us are really necessary. If I remember correctly, I have seen this direct connection of caps to supply when working in other places, but I do not have any realibility/manufacturability info to say if that caused problems or not.

I suggest that we take discussions on this secondary topic offline.

Regards
Vivek